Deposition and patterning are two of the basic steps performed in semiconductor processing. Patterning is also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of deposition. Alignment is critical in photo-lithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Therefore, alignment marks are placed on the semiconductor wafer for the proper positioning during the deposition and photolithography processes.
Alignment is especially critical where a number of layers have already been deposited on the wafer. Subsequent deposition of other layers in such instances usually requires that the alignment marks on the wafer be exposed for proper overlay of the silicon dioxide or other layers. Overlay accuracy within photolithography becomes more stringent as the critical dimensions (CD's) and other dimensions of the semiconductor designs become smaller and smaller.
Currently, the control of overlay alignment is accomplished by the alignment systems of scanners performing overlay corrections for inter-field overlay and reticle expansion, and feed-forward overlay corrections by the box-in-box overlay results of previous lots for any remaining inter- and intra-field errors. Examples of inter-field and intra-field errors are shown in FIGS. 1 and 2, respectively.
In FIG. 1, the inter-field overlay errors within the semiconductor wafer 100 are represented by the arrows 102. The arrows 102 represent inter-field overlay translation errors in both the x and y directions, wafer expansion errors in both the x and y directions, wafer rotation, and non-orthogonal errors. That is, the arrows 102 represent overlay errors between fields. In FIG. 2, the intra-field overlay errors within the wafer 200 are represented by the arrows 202. The arrows 202 represent intra-field overlay translation errors in both the x and y directions, reticle field rotation and reticle asymmetric field rotation errors, and reticle magnification and reticle asymmetric magnification errors. That is, the arrows 202 represent overlay errors within a field.
The disadvantage with current overlay alignment—that is, corrections by the alignment system of the scanners and feed-forward overlay corrections—is that there is no ability to perform in-situ, or in-place, overlay corrections for the intra-field wafer errors. The intra-field errors are corrected in a feed-forward process, which is a passive process. This can result in out-of-specification overlays, resulting in sometimes costly and time-consuming semiconductor rework.
Therefore, there is a need for performing in-situ overlay corrections, especially for intra-field semiconductor wafer errors. There is a need for such correction to be performed without having to resort to a feed-forward process. Such a new, in-situ, approach to overlay correction should result in a reduction of out-of-specification overlays, reducing costly and time-consuming semiconductor rework. For these and other reasons, there is a need for the present invention.